1. Field of the Invention
The invention involves a defect tolerant memory for a computer system. More specifically, the defect memory has a redundant memory and mask memory which use randomness techniques for storing respectively redundant information and addresses of defects.
2. Description of the Prior Art
As memory density and the size of the chips in the memories increase, the number of defects in the memory and chip also increases. An example is a state-of-the-art 128K memory having 60 bit words which uses 480 16K memory chips. It is impractical to attempt to procure and use 16K chips with no defects. To provide for correction of defective cells in the memory chips there must be a means for storing the locations of such defects and also for storing information redundant to that in the defective locations.
U.S. Pat. No. 4,051,354 dicloses a chip which performs such a function. In this patent, a chip array has redundant rows and/or columns of cells and a programmed logic array for decoding the addresses of defective cells. A redundant column (or row) may contain redundant information for various defective cells occurring randomly in different rows (or columns) of the main columns of the array. This is a randomness technique expecting one or less defects per row per redundant column. The patent uses this technique for single bit defects in single chips. If multiple chips are used, as in a multi-chip memory, each of the chips must have similar redundant rows/columns and circuitry. This arrangement becomes complex and costly for large memories. Furthermore, if defect randomness exceeds the capability of the chip redundancy the chip is scrapped.